The present invention relates to an operational amplifier circuit, and more particularly, it relates to an operational amplifier circuit for fixing an offset voltage to a constant value in an output dynamic range.
Recently, with respect to liquid crystal panels and organic EL panels particularly for use in portable equipment, compact mobile equipment and large panel equipment, there are increasing demands for an operational amplifier circuit capable of outputting a constant offset in a wide output voltage range with small power consumption. In conventional technique, an operational amplifier circuit is generally used for realizing a wide output voltage range, but it has been impossible to fix an offset to a constant value in a wide output range because of restriction in the circuit configuration.
A conventional operational amplifier circuit will now be described with reference to FIG. 18. The operational amplifier circuit roughly includes three parts, that is, an input stage, a phase compensating part and an output stage. The operational amplifier circuit receives bias voltages VBP0, VBP1, VBP2, VBP3, VBP4, VBN0, VBN1, VBN2, VBN3 and VBN4 from a bias circuit for performing a given operation.
Offset specialization of the conventional operational amplifier circuit will now be described with reference to FIGS. 10A through 10E. A waveform of FIG. 10A is obtained when an input voltage INP is changed from a potential resulting from addition of an overdrive voltage to a voltage AVSS to a potential resulting from subtraction of the overdrive voltage from a voltage AVDD. At this point, a current flowing to a transistor MP1, that is, a PMOS current source of the input stage, is indicated by Idp1 and a current flowing to a transistor MN1, that is, an NMOS current source, is indicated by Idn1. A waveform of FIG. 10B shows a current characteristic of the current Idp1 flowing to the PMOS transistor MP1 when the voltage INP is changed from the potential resulting from the addition of the overdrive voltage to the voltage AVSS to the potential resulting from the subtraction of the overdrive voltage from the voltage AVDD. In a period t3, no current flows because PMOS differential pair transistors MP2 and MP3 are in an off state. A waveform of FIG. 10C shows a current characteristic of the current Idn1 flowing to the NMOS transistor MN1 when the voltage INP is changed from the potential resulting from the addition of the overdrive voltage to the voltage AVSS to the potential resulting from the subtraction of the overdrive voltage from the voltage AVDD. In a period t1, no current flows because transistors MN2 and MN3 are in an off state.
A waveform of FIG. 10D shows a current characteristic obtained as a sum of the current characteristics of the currents Idp1 and Idn1 obtained when the voltage INP is changed from the potential resulting from the addition of the overdrive voltage to the voltage AVSS to the potential resulting from the subtraction of the overdrive voltage from the voltage AVDD. In the period t1, since the NMOS current source MN1 is halted, a current value obtained as a sum of the currents Idp1 and Idn1 is equal to the current value of the current Idp1. In a period t2, since both the NMOS current source MN1 and the PMOS current source MP1 are operated, a current value obtained in this period is equal to a current value obtained as the sum of the currents Idp1 and Idn1. In the period t3, since the PMOS current source MP1 is halted, a current value obtained as the sum of the currents Idp1 and Idn1 is equal to the current value of the current Idn1.
A waveform of FIG. 10E shows an offset characteristic obtained when the voltage INP is changed from the potential resulting from the addition of the overdrive voltage to the voltage AVSS to the potential resulting from the subtraction of the overdrive voltage from the voltage AVDD. Owing to the characteristic of an ideal operational amplifier, a gain is larger and an offset value is smaller when a current obtained as the sum of the currents Idp1 and Idn1 is larger. On the other hand, when the current is smaller, the gain is smaller and the offset value is larger. Specifically, based on the current characteristic obtained as the sum of the currents Idp1 and Idn1 shown in FIG. 10D, the offset value is larger in the periods t1 and t3 and is smaller in the period t2. In other words, since the gain of the input stage is varied in accordance with the input voltage value, the offset value is also varied in accordance with the input voltage value, and thus, a constant offset cannot be realized.